Method and apparatus for dual rail SRAM level shifter with latching
US9058858B2 · kind B2 · utility
3Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2011 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Oct 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.