Control circuitry for memory cells
US9058888B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2012 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Jan 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.