DRAM refresh
US9058896B2 · kind B2 · utility
4Cited by
15References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2012 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Dec 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.