Apparatus for reducing read latency by adjusting clock and read control signals timings to a memory device
US9058898B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 21, 2014 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Apr 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an efficient way to read data from a memory device by aligning an internal clock of the memory interface circuit with the read data strobe signal from the memory device by delaying the internal clock along with control signals for reading the memory device before transmitting them to the memory device, wherein the internal clock of the memory controller can sample the read data from the memory device directly without using a FIFO device between the internal clock and the read data strobe so as to reduce latency of reading data from the memory device. For example, the memory device can be a double-data-rate (DDR) DRAM device, and the control signals includes command and address signals of the DDR DRAM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.