Nonvolatile semiconductor device and its manufacturing method having memory cells with multiple layers
US9059035B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2012 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Dec 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.