Stacked semiconductor device and printed circuit board
US9059084B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Dec 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interposer of a first semiconductor package includes a power supply wiring for a second semiconductor element, the power supply wiring including a land provided in one surface layer, and a power supply pattern provided in an inner layer and electrically connected to the land, the power supply wiring further including a larger number of lands than the land, which are provided in another surface layer and electrically connected in parallel to the power supply pattern. In a stacked semiconductor device, this configuration can improve the quality of power supply to the second semiconductor element to secure signal processing operation while preventing an increase in inductance caused by the bending of a power supply path in a power supply wiring of a printed wiring board or by a deviation of connection intervals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.