Routing layer for mitigating stress in a semiconductor die
US9059159B2 · kind B2 · utility
4Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Dec 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.