Enhanced stress memorization technique for metal gate transistors

US9059210B2 · kind B2 · utility

Assignees

• Semiconductor Manufacturing International (Beijing) Corporation · CN
• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventor

• Yong Li · Chaole, CN

Key dates

• Filing date: Mar 27, 2014
• Grant date: Jun 16, 2015
• Expiry date: Mar 27, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/022

Abstract

A method of manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor substrate, forming sidewall spacers, and forming heavily doped source/drain regions. After removing the spacers, a stress material layer is formed over the dummy gate structure. An annealing process is performed to transfer the stress to the device channel region. After the annealing process, the stress material layer is removed. The dummy gate structure is replaced by a high-k dielectric layer and a metal gate structure. Subsequently, contact holes are formed to expose at least part of the heavily doped source/drain regions, and self-aligned silicide is formed over exposed portions of the heavily doped source/drain regions.