Array substrate and its manufacturing method
US9059293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Aug 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
An array substrate comprises a substrate, a gate electrode, a source electrode and a drain electrode, the source electrode and the drain electrode being provided in different areas on the substrate and the vertical projections of the source electrode and the drain electrode on the substrate having an overlapping area; a semiconductor layer formed between the source electrode and the drain electrode, a vertical projection of the semiconductor layer on the substrate having overlapping areas with the vertical projections of the source electrode and the drain electrode on the substrate; a first insulating layer formed on the substrate while below the gate electrode and covering the source electrode or the drain electrode; a pixel electrode, a gate line, and a data line. A manufacturing method for the array substrate is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.