SRAM devices utilizing strained-channel transistors and methods of manufacture

US9059310B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Harry-Hak-Lay Chuang · Austin, US
• Hung-Chih Tsai
• Kong-Beng Thei · Baoshan, TW
• Mong-Song Liang · Baoshan, TW

Key dates

• Filing date: Dec 10, 2013
• Grant date: Jun 16, 2015
• Expiry date: Dec 10, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0184

Abstract

A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.