3D package device of photonic integrated chip matching circuit
US9059516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2012 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Oct 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01P11/003
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A 3D package device of a photonic integrated chip matching circuit, comprising: a first carrier substrate; a first microwave transmission line array formed by evaporation on the top surface of the first carrier substrate to provide bias voltages and high-frequency modulation signals to the photonic integrated chip; a second carrier substrate formed perpendicularly to the first carrier substrate or to have a certain angle with respect to the first carrier substrate, so as to constitute a 3D structure; a second microwave transmission line array formed by evaporation on the bottom surface of the second carrier substrate to match electrodes of the first microwave transmission line array, the second microwave transmission line array being soldered or sintered with the electrodes of the first microwave transmission line array; an electrode array formed by evaporation on a side surface or two opposite side surfaces of the second carrier substrate; and a microwave circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.