False-triggered immunity and reliability-free ESD protection device
US9059582B2 · kind B2 · utility
1Cited by
1References
20Claims
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Key dates
| Filing date | Mar 1, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Oct 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An acceptable voltage margin between a voltage level for triggering electrostatic current discharge and a voltage level for programming operation of an OTP device is determined. Activation of an ESD protection circuit is controlled in part in response to a false trigger prevention circuit. To avoid gate oxide breakdown that may occur with a MOSFET protection device used for higher voltage requirements of an OTP device, the ESD protection circuit employs a bipolar transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.