Differential decoder
US9059724B2 · kind B2 · utility
5Cited by
18References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2014 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Feb 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M5/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.