Memory device
US9061898B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2012 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Sep 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/881
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
According to one embodiment, a memory device includes the following structure. A first double tunnel junction structure includes a first nanocrystal layer that includes first conductive minute particles, and first and second tunnel insulating films arranged to sandwich the first nanocrystal layer. A second double tunnel junction structure includes a second nanocrystal layer that includes second conductive minute particles, and third and fourth tunnel insulating films arranged to sandwich the second nanocrystal layer. A charge storage layer is arranged between the first and second double tunnel junction structures. First and second conductive layers are arranged to sandwich the first double tunnel junction structure, the charge storage layer, and the second double tunnel junction structure. The first conductive minute particles has an average grain size which is different from that of the second conductive minute particles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.