Method and apparatus for improving processing performance of a multi-core processor
US9063796B2 · kind B2 · utility
10Cited by
8References
16Claims
0Family size
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Key dates
| Filing date | Aug 2, 2012 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Jul 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Managing task execution in a multi-core processor may be achieved by employing a spinlock and a multi-processor priority ceiling protocol. The spinlock may be employed to effect a dynamically enforceable mutual exclusion constraint. The multi-processor priority ceiling protocol may be employed to effect the dynamically enforceable mutual exclusion constraint to synchronize a plurality of tasks executing in the first and second processing cores of the multi-core processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.