Memory controller load balancing with configurable striping domains
US9063825B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 20, 2010 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Feb 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Managing data in a computing system comprising a plurality of cores includes: assigning an address within a memory address space for access by one of a plurality of memory controllers coupled to different respective cores based on a designated portion of the address. The designated portion is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address. In response to a memory access request at one of the cores to access data stored at the address, the system determines which of the plurality of memory controllers to which the memory access request is to be directed based on the designated portion of the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.