System and method for secure mode for processors and memories on multiple semiconductor dies within a single semiconductor package
US9063889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2004 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Oct 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system comprising a processor having a first and second bus (the processor on a first semiconductor die mounted within a semiconductor package), a monitoring device coupled to both the first and second bus of the processor (the monitoring device on the first semiconductor die mounted within the semiconductor package), a memory coupled to the processor via the first bus (coupled to the monitoring device via a security signal, the memory on a second semiconductor die mounted within the semiconductor package), and a user interface external of the semiconductor package (the user interface coupled to the processor via the second data and instruction bus). The monitoring device checks one or both of the first and second busses to determine whether a secure mode entry sequence is delivered to the processor. The first bus and the security signal are only coupled to and accessible by devices within the semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.