Quantum gate optimizations
US9064067B2 · kind B2 · utility
11Cited by
2References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 6, 2012 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Aug 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are systems and methods for improving quantum computation simulation execution time by “growing” sets of small quantum gates into larger ones. Two approaches are described. In the first approach, sub-strings may be replaced by a single representative that may be used multiple times throughout the quantum circuit. In the second approach, nearby gates may be coalesced in an iterative fashion, to thereby build larger and larger gates. Results may be cached for re-use. Both of these approaches have proven effective and have gained typical simulation speed-ups of 1-2 orders of magnitude.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.