Image sensor with hybrid heterostructure
US9064769B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 8, 2013 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Aug 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/199
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image sensor architecture for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer includes the photodiode and amplifier circuitry for each pixel. A bottom includes the pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a process optimized for forming low-noise pixels, the pixel performance can be greatly improved. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a process which has been optimized for circuit speed and manufacturing cost. By combining the two layers into a stacked structure, the top layer (and any intermediate layer(s)) acts to optically shield the lower layer, thereby allowing charge to be stored and shielded without the need for a mechanical shutter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.