Post-etch treating method
US9064819B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2011 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | May 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76814
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to a post-etch treating method. An opening is formed by etching a stacked structure of a dielectric layer, an intermediate layer and a metal hard mask layer arranged in order from bottom to top. The treating method sequentially comprises steps of: performing a first cleaning process on the stacked structure with the opening so as to remove at least a part of the metal hard mask layer; and performing a second cleaning process on the stacked structure with the opening so as to remove etching residues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.