Assembly and a chip package
US9064861B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2013 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Mar 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An assembly (60) includes a substrate (1) that is provided with at least one electrical contact (3a), a flexible printed circuit membrane (51) including an electrically insulating film (6) and an electrically conducting layer (7) that is at least partially covering the insulating film (6). The conducting layer (7) is at least locally accessible from outside of the membrane (51). A connection element (10) is provided for electrically connecting the at least one electrical contact (3a) and the conducting layer (7) at a position where the conducting layer (7) is accessible, to form an electrical connection between the substrate (1) and the membrane (51). A chip package (70) includes a housing (15) having at least one electrically conducting terminal, and an assembly (60) as mentioned. The flexible printed circuit membrane (51) is arranged for electrically connecting the substrate and the at least one terminal of the housing (15).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.