Array substrate and method of fabricating the same
US9064905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2013 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Jun 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
An array substrate includes a substrate; an oxide semiconductor layer on the substrate, the oxide semiconductor layer including an active area and source and drain areas at both sides of the active area; a gate insulating layer and a gate electrode sequentially on the active area of the oxide semiconductor layer; an inter insulating layer on the gate electrode and having first and second semiconductor contact holes that expose the source and drain areas respectively; and source and drain electrodes on the inter insulating layer and contacting the source and drain areas through the first and second semiconductor contact holes, respectively, wherein the first and second semiconductor contact holes are disposed in two regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.