Network interface and method of aggregating processor circuits
US9065747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Dec 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system having a first and second interfaces is described. At least one of the first and second interfaces has a cell engine, a first processor circuit, a second processor circuit, and a first and second transponder. The first processor circuit is coupled with the first transponder and the cell engine so as to transmit a header cell to the cell engine. The second processor circuit is coupled with the second transponder and the cell engine so as to transmit a body cell to the cell engine. The system may aggregate the processing capacity of several processor circuits to form larger capacity logical interfaces. Packets may be fragmented into a header cell including the packet header and body cells including the packet payload and then transmit and reassemble the packet. The header cells may be fully handled by the processor circuit, while body cells may be passed on without processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.