Method and apparatus for multiple access of plural memory banks
US9065860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2012 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Feb 13, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor with on-chip memory including a plurality of physical memory banks is disclosed. The processor includes a method, and corresponding apparatus, of enabling multi-access to the plurality of physical memory banks. The method comprises selecting a subset of multiple access requests to be executed in at least one clock cycle over at least one of a number of access ports connected to the plurality of physical memory banks, the selected subset of access requests addressed to different physical memory banks, among the plurality of memory banks, and scheduling the selected subset of access requests, each over a separate access port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.