Integrated level shifting latch circuit and method of operation of such a latch circuit
US9069652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2013 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Aug 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.