Memory read-channel with selective transmission of error correction data
US9069687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2010 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | May 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/15
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.