Fully parallel encoding method and fully parallel decoding method of memory system
US9069692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2013 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Nov 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.