Methods and systems to reduce display artifacts when changing display clock rate
US9070198B2 · kind B2 · utility
4Cited by
0References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2012 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Oct 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.