Memory sharing system and memory sharing method
US9070420B2 · kind B2 · utility
3Cited by
10References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2011 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Oct 12, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory sharing system includes a master control device, a slave control device and a memory device. The master control device selectively generates a clock signal to the memory device. The slave control device receives and tracks the clock signal via a delay phase locked loop (DLL) to generate and align an output signal with the clock signal. The master control device arbitrates an access right.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.