Non-volatile memory system with reset verification mechanism and method of operation thereof
US9070441B2 · kind B2 · utility
37Cited by
3References
20Claims
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Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Jul 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.