Method of patterning a semiconductor device having improved spacing and shape control and a semiconductor device
US9070688B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 15, 2013 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Oct 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 μm−1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.