Semiconductor device with low-lifetime region
US9070737B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2012 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Dec 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/112
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a p+ collector region in the surface of an n− drift region. The p+ collector region forms a p-n junction with the n− drift region. A collector electrode is in contact with the p+ collector region. A low-lifetime region having a carrier lifetime shorter than in other regions is provided, extending from the n− drift region to the p+ collector region, at the interface between the n− drift region and p+ collector region. The low-lifetime region, being partially activated in accordance with the concentration distribution of a p-type impurity implanted in order to form the p+ collector region, is in a barely activated state. The low-lifetime region has an activation rate lower than that of the p+ collector region. The p+ collector region is completely electrically activated as far as a depth of, for example, 0.5 μm-0.8 μm, from the surface on the collector electrode side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.