Electroplating methods for fabricating integrated circuit devices and devices fabricated thereby
US9070752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2014 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Jun 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.