Method for link resets in a SerDes system
US9071256B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2014 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Jun 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include grouping one or more lane modules associated with an integrated circuit (IC) together to form a link, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator. The method may also include providing a common module having a common reset release state machine and a reset release synchronizer and pulse generator, the common module and one or more lane modules being configured to communicate therebetween. The method may further include resetting each link independently using the one or more lane modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.