Data-processing device and data-processing method
US9071276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2012 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Jul 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/34
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present technology relates to a data-processing device and a data-processing method, which are capable of improving tolerance for an error of data.When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i+1)-th bit from a most significant bit of code bits of 4×2 bits and a (#i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for LDPC codes having coding rates of 1/5, 4/15, and 1/3, b0 is allocated to y4, b1 is allocated to y3, b2 is allocated to y2, b3 is allocated to y1, b4 is allocated to y6, b5 is allocated to y5, b6 is allocated to y7, and b7 is allocated to y0. For example, the present invention can be applied to a transmission system that transmits an LDPC code or the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.