Systems and methods for handling interrupts during software design simulation

US9075639B1 · kind B1 · utility

Assignee

• Altera Corporation · US

Inventor

• Yi Ni · Heidelberg, DE

Key dates

• Filing date: Oct 23, 2012
• Grant date: Jul 7, 2015
• Expiry date: Jan 28, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2117/08
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Disclosed are apparatus and methods for simulating a software design that is to be implemented in a system. A co-simulation platform comprising a physical link coupling a first physical component with a models module is provided. The models module emulates one or more other physical components of the system, and such models module includes a processor model associated with an interrupt service routine (ISR) for handling an interrupt on an interrupt line of the first physical component. Via a physical link, an interrupt request from the interrupt line of the first physical component is received into the models module. In response to the received interrupt request, the ISR associated with the processor model is initiated. Prior to exiting the ISR, an interrupt line de-assert request is sent from the models module to the first physical component via the physical link. Prior to exiting the ISR and prior to receiving a physical de-assertion of the interrupt line from the first physical component via the physical link, the models module generates a premature de-assertion of the interrupt line and causes such premature de-assertion to be received by the processor model.