Method for optimizing electrodeposition process of a plurality of vias in wafer
US9075941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2013 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jun 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The presently claimed invention provides a method for optimizing an electrodeposition process of a plurality of vias in a wafer. Instead of simulating a large number of via on the wafer for via filling, a representative via is selected with the maximum value of critical factor, which is a function of process parameters. The filling of the representative via is simulated with different sampling points to find out the filling goodness in order to find out the optimized process windows of process parameters. An optimizer is also disclosed, which either provides sampling points or reduces sampling points under artificial neural network method. Calculation of filling goodness is used for evaluating via filling quality and further comparing among via fillings simulated at different sampling points. Consequently, the method of present invention is able to shorten the simulation time for via filling as well as provide a process window with high accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.