System and method for performing depth testing at top and bottom of graphics pipeline
US9076265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2006 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Oct 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a system and method including graphics processing of a pixel sample are described. According to an embodiment, a first depth test processes a value, such as a z/stencil value, of a pixel sample and determines whether the value of the pixel sample satisfies the first depth test. If the value of the pixel sample satisfies the first depth test, the value of the pixel sample is not immediately written to storage, such as a Z-buffer. That is, if the value of the pixel sample satisfies the first depth test, the depth processing logic prevents or delays a write operation for the value of the pixel sample to storage at that time. A second depth test is performed on the value of the pixel sample if the value of the pixel sample satisfied the first depth test. If the value of the pixel sample satisfies the second depth test, the value of the pixel sample is then written to storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.