Charge sharing in a TCAM array
US9076527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2011 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Sep 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.