Non-volatile write buffer data retention pending scheduled verification
US9076530B2 · kind B2 · utility
37Cited by
3References
25Claims
0Family size
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Key dates
| Filing date | Feb 7, 2013 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jun 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (NV) buffer is adapted to store input write data having a selected logical address. A write circuit is adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer. A verify circuit is adapted to perform a verify operation at the conclusion of a predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. The input write data are retained in the NV buffer until successful transfer is verified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.