Thin film transistor array panel and method of manufacturing the same
US9076691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2013 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jul 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/38
Abstract
A method of manufacturing a thin film transistor array panel includes: a gate insulating layer disposed on a gate electrode, a semiconductor disposed on the gate insulating layer, a source electrode opposite a drain electrode disposed on the semiconductor, a color filter disposed on the gate insulating layer, an overcoat disposed on the color filter and including an inorganic material. A first dry etching is performed using the photosensitive film pattern as a mask to etch the overcoat and provide a preliminary contact hole, through which a portion of the color filter is exposed. A second dry etching is performed using the overcoat as a mask to etch the color filter through the preliminary contact hole and to provide a contact hole, through which a portion of the drain electrode is exposed. A pixel electrode is connected to the drain electrode through the contact hole, on the overcoat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.