Method for tuning the effective work function of a gate structure in a semiconductor device
US9076726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2013 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Dec 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for tuning the effective work function of a gate structure in a semiconductor device is described. The semiconductor device is part of an integrated circuit and the gate structure has a metal layer and a high-k dielectric layer separating the metal layer from an active layer of the semiconductor device. The method includes providing an interconnect structure of the integrated circuit on top of the gate structure, the interconnect structure comprising a layer stack comprising at least a pre-metal dielectric layer comprising a metal filled connecting via connected to the gate structure through the pre-metal dielectric layer, and the interconnect structure having an upper exposed metal portion; and, thereafter, exposing at least a portion of the upper exposed metal portion to a plasma under predetermined exposure conditions, to tune the effective work function of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.