Asymmetric high-voltage JFET and manufacturing process

US9076880B2 · kind B2 · utility

Assignee

• AMS AG · AT

Inventors

• Martin Knaipp · Kufstein, AT
• Georg Roehrer · Lebring, AT

Key dates

• Filing date: Jan 26, 2012
• Grant date: Jul 7, 2015
• Expiry date: Jan 2, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/126

Abstract

A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a shallow well of a first type of conductivity arranged in the further well, a first contact region for source and a second contact region for drain arranged in the further well, a third contact region for gate arranged between the first contact region and the second contact region in the shallow well, a first distance between the first contact region and the third contact region being smaller than a second distance between the second contact region and the third contact region, and an electrical connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well.