Robust flexible logic unit
US9077339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2014 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jul 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.