Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer
US9081666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2013 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Sep 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface. The non-volatile memory device interface may be configured to couple the system to one or more non-volatile memory devices. The micro-sequencer is generally coupled to (i) the control processor and (ii) the non-volatile memory device interface. The micro-sequencer includes a control store readable by the micro-sequencer and writable by the control processor. In response to receiving a particular one of the commands, the control processor is enabled to cause the micro-sequencer to begin executing at a location in the control store according to the particular command and the micro-sequencer is enabled to perform at least a portion of the particular command according to a protocol of the one or more non-volatile memory devices coupled to the non-volatile memory device interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.