Method for wear leveling in a nonvolatile memory
US9081671B2 · kind B2 · utility
3Cited by
8References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2014 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Jun 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.