Data accessing method to boost performance of FIR operation on balanced throughput data-path architecture
US9082476B2 · kind B2 · utility
0Cited by
2References
21Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jul 8, 2013 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Jan 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are disclosed to implement digital signal processing operations involving multiply-accumulate (MAC) operations, by using a modified balanced data structure and accessing architecture. This architecture maintains a data-path connecting one address generation unit, one register file and one MAC execution unit. The register file has a hierarchical grouping organization of individual registers, which reduces bubble cycles caused by memory misalignments. This architecture uses parallel execution and can achieve two or more MAC operations per cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.