Method and apparatus for reading variable resistance memory elements
US9082509B2 · kind B2 · utility
1Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2012 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Dec 19, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, detecting resistance in a resistive memory cell may be done using a pulse edge. For example, a pulse may be applied through a resistive memory data cell and another through a reference delay circuit to determine which path has the larger delay in order to determine the resistive state of the data cell in question.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.