Integrated circuits with laterally diffused metal oxide semiconductor structures
US9082846B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2013 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Sep 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with improved LDMOS structures are provided. An integrated circuit includes a semiconductor substrate, a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor structure. The transistor structure includes a gate dielectric positioned over a portion of a first one of the plurality of STI regions, a drain region adjacent to the first one of the plurality of STI regions and spaced apart from the gate dielectric, a first gate electrode that extends over a first portion of the gate dielectric, a second gate electrode that extends over a second portion of the gate dielectric and positioned adjacent to the first gate electrode, and a source region positioned adjacent to the first portion of the gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.