Method for preparing an N+PP+ or P+NN+ structure on silicon wafers

US9082924B2 · kind B2 · utility

Assignees

• EDF ENR PWT · FR
• SYNERGIES POUR EQUIPEMENTS MICRO-ELECTRONIQUE COMMUNICATION OPTIQUE SA · FR
• INSTITUT NATIONAL DES SCIENCES APPLIQUÉES DE LYON · FR
• CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE · FR

Inventors

• Barbara Bazer-Bachi · Villate, FR
• Mustapha Lemiti · Val-de-Reuil, FR
• Nam Le Quang · Bourgoin-Jallieu, FR
• Yvon Pellegrin · Frontignan, FR

Key dates

• Filing date: Apr 26, 2011
• Grant date: Jul 14, 2015
• Expiry date: Dec 20, 2031

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P70/50
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention relates to a method for preparing, on a silicon wafer, an n+pp+ or p+nn+ structure which includes the following consecutive steps: a) on a p or n silicon wafer (1), which includes a front surface (8) and a rear surface (9), a layer of boron-doped silicon oxide (BSG) (2) is formed on the rear surface (9) by PECVD, followed by a SiOx diffusion barrier (3); b) a source of phosphorus is diffused such that the phosphorus and the boron co-diffuse and in order also to form: on the front surface (8) of the wafer obtained at the end of step a), a layer of phosphorus-doped silicon oxide (PSG) (4) and an n+ doped area (5); and on the rear surface of the wafer obtained at the end of step a), a boron-rich area (BRL) (6), as well as a p+ doped area (7); c) the layers of BSG (2) and PSG (4) oxides and SiOx (3) are removed, the BRL (6) is oxidized and the layer resulting from said oxidation is removed. The invention also relates to a silicon wafer having an n+pp+ or p+nn+ structure, which can be obtained by said preparation method, as well as to a photovoltaic panel manufactured from such a silicon wafer.